The present invention relates to a semiconductor integrated circuit device which matches the trend toward further miniaturization and to a method for designing the same.
If a plurality of functional blocks are formed in one chip, it has not been performed conventionally to provide MOS transistors contained in a plurality of digital functional circuit blocks with different gate lengths or provide the respective gate oxide films of the MOS transistors with different thicknesses.
Briefly, in a conventional circuit designing method, on-chip micro-patterning is regulated by one design rule and a reduction in margin resulting from patterning variations is compensated for by using a uniform value. The reason for a uniform margin allowed is that a difference of one order of magnitude or more exists between a required performance value and a required margin. In an exemplary case, a specification for a required access time is 3.0 ns, a mean value of actually obtained access times is 2.5 ns, and a required margin considering patterning variations is 0.3 ns. In the case where the specification for the required access time is set to 0.4 ns, however, if the mean value of actually obtained access times is improved to 0.25 ns and a margin of 0.30 ns is allowed, the improvement in performance is suppressed by the margin for patterning variations.
This indicates that, as increasingly higher performance is required in future, if a uniform margin for patterning variations is provided throughout the entire chip, an improvement in performance is suppressed by the uniform margin.
In other words, it becomes difficult to satisfy required performance throughout the entire chip, though the required performance is satisfied locally in a portion of the chip. As a result, the performance of the chip is limited by the worst portion of the entire chip so that the performance is not improved.
In an analog circuit or a circuit for which consideration should be given to a latch-up caused by an electrostatic damage (ESD) or to a breakdown voltage, it has been a conventional practice to use different design rules for a transistor provided on the I/O pad portion of the circuit and for the logic portion of the circuit. This is because different power supply voltages are applied thereto.
Thus, it has not been performed conventionally to use different design rules in one digital circuit block or in one analog circuit. It has not been performed, either, to divide one wafer into chips of different sizes or fabricate, from one wafer, various chips designed to have different functions or performances on a per chip basis.
As design sizes are reduced increasingly year after year, the design of a chip performed by applying one design rule to one chip encounters the following problems.
The design rule which is 0.13 μm in the year 2001 is expected to become 0.10 μm in the year 2005. If design is to be performed in accordance with the design rule of 0.10 μm, a fabrication process requires a patterning accuracy on the order of several tens of nanometers.
In that case, it will become extremely difficult to control variations in patterning accuracy to several tens of nanometers in consideration of each of variations in patterning accuracy in the fabrication process depending on the regions of the principal surface (portion) of a wafer, the relationship between the regions (portions) of one chip and layout densities therein, and the like.
If design rules also considering variations in patterning accuracy are applied, a design margin is reduced dramatically so that the yield rate is reduced significantly. As a consequence, the trend toward further miniaturization drastically increases the manufacturing cost for a chip.